kernel: a real timer source (64 Hz tick IRQ) + uptime(1)

The kernel had no clock: TimerISR was a reti stub, IEF_TIMER masked, and
IME was never enabled - the vectors were decorative. sys_sleep just polls
DIV deltas per-process; nothing counted globally.

Now: TAC runs the hardware timer at 16384 Hz with TMA=0, so TIMA overflows
at exactly 64 Hz; TimerISR increments a monotonic 32-bit wTicks (wraps
after ~2.1 years). Scheduling stays cooperative - the ISR is transparent.

Enabling IME in a kernel written for zero interrupts needs care wherever
SP points into memory whose bank is being switched (an IRQ pushes onto SP):
  - read_block/write_block map the disk bank over the $A000 window that
    holds the caller's stack -> di/ei around the transfer (~2ms, well under
    the 15.6ms tick period, so no tick is ever lost)
  - hSwitchTo switches SVBK + cart-RAM banks under the outgoing stack ->
    di on entry, ei once the incoming stack is mapped
  - fork already runs on KSTACK_TOP2 (fixed WRAM) - safe as-is
  - term_putc's SVBK switch only remaps $Dxxx, stacks live in $Axxx/$Cxxx

SYS_UPTIME (36) copies the counter (4B LE, di/ei so the read can't tear)
to a user buffer; libc gticks(); usr/uptime.c formats 'up [Nd] H:MM:SS'.
uptime avoids SDCC long div/shift entirely: sm83.lib modules link into
their own areas that land in the $A000 RAM window (latent build.sh trap,
documented there) - bytewise >>6 plus bounded subtraction loops instead.

1 files changed, 5 insertions, 0 deletions

diff --git a/src/hram.asm b/src/hram.asm
index 7c1910c..9e65982 100644
--- a/src/hram.asm
+++ b/src/hram.asm
@@ -31,6 +31,9 @@ LOAD "hram_code", HRAM
 ;   Runs from HRAM.  Saves/restores full context.  Clobbers everything.
 ; ---------------------------------------------------------------------------
 hSwitchTo::
+    di                          ; no tick ISR while SP and the banks under it
+                                ; are out of sync (pushes would hit the wrong
+                                ; bank); ei below once the incoming stack is up
     ; stash target while DE is still valid
     ld a, e
     ld [hSwitchTgt], a
@@ -114,6 +117,8 @@ hSwitchTo::
     ld sp, hl
 
     ; --- pop incoming context and resume it ---
+    ei                          ; SP + banks consistent again (takes effect
+                                ; after the next instruction)
     pop hl
     pop de
     pop bc