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authoruser <user@clank>2026-07-18 21:56:21 +0200
committeruser <user@clank>2026-07-18 21:56:21 +0200
commitbea52bc8f99ee6dbcc8154a366560fc18e7b24c8 (patch)
tree0772b5d9e98de7f6c495198844c230537c7fb9d6 /src/hram.asm
parentterm: SCY ring-scroll - scroll writes ONE map row; OSK toggle is 212 cycles (diff)
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term: latch SCY in VBlank - fix ring-scroll shear on live displays
The ring-scroll wrote SCY mid-frame; SCY is sampled per scanline (on hardware and in sl0pboy's PPU), so a scroll landing mid-frame rendered the top of the frame at the old offset and the bottom at the new one - a one-frame shear, invisible in frame-sampled GIF captures but ugly on a live sixel view. term_view_update now writes hSCY (HRAM) and a transparent VBlank ISR (push af / apply / pop af / reti, same profile as TimerISR) copies it to rSCY, so the view only ever moves at frame boundaries. The scroll's tile+map writes stay immediate: the new map row is invisible at the old SCY by construction (it's the ring row one past the visible 18).
Diffstat (limited to '')
-rw-r--r--src/hram.asm4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/hram.asm b/src/hram.asm
index 9e65982..facccd0 100644
--- a/src/hram.asm
+++ b/src/hram.asm
@@ -17,6 +17,10 @@ SECTION "hram_vars", HRAM
hCurBankRAM: DS 1 ; shadow of active cart-RAM bank
hCurBankWRAM: DS 1 ; shadow of active SVBK bank
hSwitchTgt: DS 2 ; &incoming PCB (set before the pushes clobber DE)
+hSCY:: DS 1 ; VBlank-latched SCY: term_view_update writes this,
+ ; the VBlank ISR applies it - a mid-frame SCY write
+ ; would shear the picture (SCY is sampled per
+ ; scanline), so ring-scrolls land at frame boundaries
; -----------------------------------------------------------------------------
; Source image (lives in ROM0); CopyHramCode blits it to HRAM at boot.