| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | MEC/PM4 round 9: stop the KIQ port on cost/benefit, name the cheaper route | user | 2026-09-28 |
| * | MEC/PM4 round 8: port amdgpu's KIQ slot selection; queue activates, still stalls | user | 2026-09-28 |
| * | MEC/PM4 round 7: HIQ plumbing blocked, blocker characterised precisely | user | 2026-09-28 |
| * | MEC/PM4 round 6: MAP_QUEUES chain is untested, not closed | user | 2026-09-28 |
| * | MEC/PM4 round 5 [HW]: the user->kernel register boundary holds | user | 2026-09-28 |
| * | MEC/PM4 round 4: correct the dispatch table, refute the length-bound guess | user | 2026-09-28 |
| * | Audit MES, PFP and ME; settle the IMU ISA as Xtensa | user | 2026-09-28 |
