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| author | user <user@clank> | 2026-07-18 22:06:35 +0200 |
|---|---|---|
| committer | user <user@clank> | 2026-07-18 22:06:35 +0200 |
| commit | 4425150cb6f52d15f513690a75645639358a2030 (patch) | |
| tree | b186e048c286f7fb9b78552fb10ebf417ac5178c /src/sched.asm | |
| parent | term: latch SCY in VBlank - fix ring-scroll shear on live displays (diff) | |
| download | gbos-4425150cb6f52d15f513690a75645639358a2030.tar.gz gbos-4425150cb6f52d15f513690a75645639358a2030.tar.xz gbos-4425150cb6f52d15f513690a75645639358a2030.zip | |
kernel: CGB double-speed mode - 2x everything (1.99x measured)
KEY1 prepare + STOP at KernelInit (skipped on warm reboot if already
fast). The PPU/LCD keep their normal rate; the timer and DIV double
with the CPU, compensated at the two consumers:
- TimerISR now fires at 128 Hz; a toggle byte keeps wTicks at 64 Hz
(uptime semantics unchanged)
- sys_sleep halves the DIV-delta accumulator's high byte (256 DIV
ticks = 1/128 s in double speed) so gsleep/msleep stay real-time
Measured: count 60 (scroll-heavy) 3.77s -> 1.89s wall; wTicks 64 Hz
over 4s; ping's 800ms msleep pacing unchanged (2.77s for 4 echoes).
sl0pboy already emulated KEY1/STOP + per-speed timer/PPU rates.
Diffstat (limited to 'src/sched.asm')
| -rw-r--r-- | src/sched.asm | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/sched.asm b/src/sched.asm index 0369ff4..b4b5a30 100644 --- a/src/sched.asm +++ b/src/sched.asm @@ -67,9 +67,10 @@ FindNextReady:: ret ; ----------------------------------------------------------------------------- -; TimerISR - the system tick. TAC runs the timer at 16384 Hz with TMA=0, so -; TIMA overflows (and this fires) at 64 Hz: wTicks is a monotonic 32-bit -; 1/64-second counter (SYS_UPTIME reads it; wraps after ~2.1 years). +; TimerISR - the system tick. TAC runs the timer at 16384 Hz with TMA=0 - +; but the CPU is in DOUBLE-SPEED mode, so the input clock is really 32768 Hz +; and this fires at 128 Hz. A toggle halves that back down: wTicks stays a +; monotonic 32-bit 1/64-second counter (SYS_UPTIME reads it; wraps ~2.1 yr). ; Scheduling stays cooperative - this ISR is deliberately transparent (all ; registers preserved, fixed-WRAM only), so it can interrupt anything, ; including kernel code mid-syscall. Preemption would hook in here later. @@ -77,6 +78,11 @@ FindNextReady:: TimerISR:: push af push hl + ld hl, wTickTog + ld a, [hl] + xor 1 + ld [hl], a + jr nz, .done ; first IRQ of the 128 Hz pair: count nothing ld hl, wTicks inc [hl] jr nz, .done ; no carry out of byte 0 |